Open the Symbol Toolbox from the View menu. Drag the symbols from the Symbol Toolbox and place it on the diagram. Click with the right-mouse button over the Symbol Toolbox window and choose Select Libraries from the shortcut menu. The contents of the Symbols Toolbox window will be updated immediately.
There are two methods of drawing wires. The first method is based on consecutive clicks and the other requires that you hold the mouse button while drawing. Go to the Diagram menu click on the Wire. Move the mouse pointer toward the point where you want to end the wire. When moving the mouse pointer, a temporary wire line will be stretched between the wire origin and the current location of the mouse pointer.
If you want to anchor a corner on the wire being drawn, click with the mouse button. Click where you want to end the wire. If you want to end the wire in empty diagram space, you must double-click instead of the single click. Move the mouse pointer to the point where you want to start drawing the wire, and then hold down the mouse button.
While holding the mouse button, move the mouse pointer toward the point where you want to end the wire. When you move the mouse pointer, a temporary wire line will be stretched between the wire origin and the current location of the mouse pointer. To anchor a corner on the wire being drawn, press Space while still holding the mouse button. Drawing new bus is similar to drawing new wire. The Testbench Wizard is designed for automatic generation of testbench files one macro file and a number of source files based on the user-defined specification.
One of the most important information entered by the user is the test vector file name. A testbench generates stimulus for the UUT entity on the basis of test vectors defined in this file. Select Generate Testbench from the Tools menu. Or from the File tab in the Design Browser , expand the branch showing the contents of the default working library or source file HDL, block or state diagram file.
Right-click the entity-architecture pair, module, or cell for which you want to generate a testbench, and then select Generate Testbench from the shortcut menu. Compilation is a process of analysis of a source file. Analyzed design units contained within the file are placed into the working library in a format understandable to the simulator.
When you choose a menu command or toolbar button for compilation, Active-HDL automatically employs the compiler appropriate for the type of the source file being compiled. If you want to compile a single file, go to the Files tab in the Design Browser , right-click the file, and choose compile from the shortcut menu. If you choose Compile All from the Design menu for a given design, the compiler automatically reorders the source files to ensure proper sequence in which design units are compiled see Figure 9.
All messages infos, warnings and errors generated during compilation are displayed in the Console window or if enabled, on the Compilation tab. Library units resulting from the compilation of a source file are placed into the working library selected for this file.
By default, all source files in the design will be compiled into the default working library. Once all needed design units have been successfully compiled, you can initialize simulation. Before you initialize simulation, make sure that:. Expand a structure of a source file containing a top-level unit or current working library in the Files tab, right-click the desired design unit and then choose Set as Top-Level from the shortcut menu. Open the Design Setting Window.
By default, the General category is displayed. Go to the Top-level category and select a top-level unit from the list of design units. You have set the desired value of simulation resolution. For this go to Settings from the Design menu. The Design Settings dialog box will open.
On the Simulation category, choose either the desire simulation resolution value or Auto. Click OK to close the dialog and complete the operation see Figure If you run the simulator without any top-level unit selected, Active-HDL will prompt you with a dialog box to select one.
To begin simulation, you must choose Initialize Simulation from the Simulation menu. The command launches elaboration and initialization of the simulation model. During elaboration, the simulator loads design units and builds the simulation model in the computer memory. During the initialization, all objects in the model signals, variables, etc.
You can run simulation for an unspecified amount of time. For that choose Run from the Simulation menu. To advance a simulation by a specific time step, set the desired time step in the Simulation Step box located in the main toolbar see Figure Specify the desired time until a simulation should run and then click OK. To pause the simulation at the current simulation time, choose the Pause option from the Simulation menu.
To finish the simulation session, choose End Simulation form the Simulation menu. You can restart the simulation, select Restart Simulation from the Simulation menu.
The Accelerated Waveform Viewer should be the pseered choice for designers working with large amounts of simulation data. It is optimized for large designs and long simulation runs. For example, it can show how the current simulation overwrites results from the previous simulation run and allows you to use hotkey stimulators.
In order to open a new waveform window, go to New Waveform from the File menu; click New Waveform on the toolbar. Before you start any simulation you must select signals that represent the input and output ports of the tested model or internal signals. To add signals to the waveform file go to the Design Browser and on the Structure tab, click on the top level design file. Right-clicking on the top level design select Add to Waveform option.
This option adds one or more selected objects to the waveform window in order they are displayed in the Design Browser , order of selection, or order resulting from both manual object multi-selection and then adding the selected signals.
You can also add all signals from the selected hierarchy and its sub regions by using the Add to Waveform Recursively option available in the context menu of the Structure tab. You can also add the signals by dragging objects from the upper or lower pane of the Structure tab to the waveform window see Figure When the simulation is finished or has run for the given time, you can save the waveform using File Save menu.
Use the restart button to reinitialize the simulation without losing the signals in the waveform. The most popular versions among the software users are 9. This PC program operates '. Thank you for using our software library. We recommend checking your downloads with an antivirus. FDM Lib takes it upon itself to provide free download links and inform users when the developing company starts providing a version of Aldec Active-HDL Student Edition for direct download.
The Active-HDL A powerful FPGA design and simulation application providing powerful collaboration features and a wide range of powerful tools. It also comes with a complete set of graphical design tools and support for multilingual simulations. Moreover, this powerful solution provides better simulation features that make it among the most prominent solutions to deal with FPGA devices.
0コメント